Gendio Display Controller
An ESP32-S3 display-controller candidate combining a custom four-layer PCB, serial data handling, matrix-display firmware and a local browser interface for configuration and maintenance.
Problem
Developing a replacement controller for an industrial weight display requires the electrical design, incoming data, display timing and commissioning workflow to agree. The original internal panel interface still needs measurement before compatibility can be established.
System boundary
An ESP32-S3 display-controller candidate combining a custom four-layer PCB, serial data handling, matrix-display firmware and a local browser interface for configuration and maintenance.
Architecture
Serial inputs feed a bounded parser and receiver state machine. Display formatting and scanning are separated from configuration and update handling. The PCB brings together power conversion, processing, serial interfaces, display buffering and a limited bench Ethernet path.
Constraints and decisions
- Kept display outputs disarmed after boot until a technician explicitly enables them. The panel interface must be checked before commissioning.
- Used synthetic protocol fixtures to exercise fragmentation, corruption, timeouts and recovery without implying compatibility with untested physical indicators.
- Reviewed footprints, connector drills and component dissipation alongside connectivity checks. Corrected a fuse footprint and increased the termination resistor rating after review.
- Added regression coverage for unsupported-character fallback and invalid display rows, including fail-blank behaviour.
- Separated bounded circuit models from full-regulator simulation. Unsuccessful vendor-model trials remain unresolved rather than being counted as passes.
Verification
The following results were recorded in the supplied engineering evidence dated 15 September 2026. They are source-record results, not new hardware tests performed for this portfolio. Assertion counts include repeated synthetic cases and are not counts of independent physical trials.
Tests, trials and findings
- Schematic and PCB rules
Zero reported ERC and DRC violations; zero unconnected items and schematic parity errors.
Recorded KiCad 10.0.6 checks with configured exclusions. Component-specific layout and assembly review remain open.
- Firmware build and image checks
ESP32-S3 build recorded successfully; offline image identity, partition placement and non-overlap checks passed.
Build and file checks only. No physical flash, boot or interrupted-update recovery test.
- Protocol and recovery tests
350 protocol assertions and 61,234 extended assertions passed across 31 synthetic profiles.
Synthetic fixtures cover fragmentation, corruption, timeouts, recovery and counter wraparound. Real indicator captures are still required.
- Display regression tests
Glyph fallback, clipping, mirroring, row addressing, clock pulses, disarming and invalid-row blanking passed.
Host framebuffer and GPIO simulation. Panel timing, brightness and electrical behaviour were not measured.
- Browser workflows
31 protocol options and five POST workflows checked; no reported JavaScript errors or mobile horizontal overflow.
Mocked API responses. Does not establish live authentication, radio operation or device update reliability.
- Bounded circuit studies
Ten ngspice studies passed their numerical bounds: divider corners, reset timing and six fixed-duty LC cases.
Idealised subcircuits. The regulator control law, radio transients and display load are excluded.
- Numerical development model
GNU Octave execution completed with three numerical assertions passing.
Analytical load-step and tolerance studies. The plotted waveform is a model response, not a board measurement.
- Regulator simulation trials
Vendor-model attempts failed to converge or produced invalid output; no validated full-regulator result.
Requires a compatible model/simulator and physical power-stage verification.
- Layout, thermal and EMC review
Supplementary findings were triaged; layout and environmental acceptance remain open.
Some automated flags were identified as false positives. The thermal report evaluated no components and is not a thermal pass.
- Mechanical and assembly checks
Board model and mounting exports prepared; 88 SMT designators matched the draft placement file.
Simplified component envelopes, unverified enclosure/harness fit and unresolved procurement prevent production acceptance.
Selected development evidence
The local interface groups commissioning and maintenance controls. This capture uses test responses with no connected board; visible values are test inputs, not deployment settings.
The load-step model oscillates and settles near 4.90 V. It excludes the regulator control loop. The state sequence is illustrative, and the corner values depend on selected study assumptions.
Current readiness
Engineering candidate. Physical bring-up and production acceptance remain outstanding.
Scope and limitations
No assembled board was available in the evidence package. Original panel mapping and timing, full-regulator behaviour, enclosure fit, procurement, thermal performance, EMC, surge, radio behaviour, update recovery and endurance remain open. Native rule checks use configured exclusions and do not establish complete design acceptance. Full schematics, PCB source, manufacturing exports, BOM, firmware and raw diagnostic records remain private.
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